1. Technical Field
Example embodiments relate generally to a memory device, and more specifically to a method of controlling a refresh operation in a memory device such as a DRAM device, capable of relieving a weak cell having poor retention characteristic.
2. Discussion of the Related Art
In a dynamic random access memory (DRAM), the electric charges charged in a cell capacitor gradually leak out of the cell capacitor. Thus, there is a need to rewrite and refresh data in a memory cell within a predetermined period. Such a refresh operation may cause power consumption so that a battery usable time of a portable electronic apparatus using a DRAM may be reduced. Thus, reduction of an average current in the refresh operation is an important factor of determining the battery usable time. Therefore, it is preferable to extend a refresh interval in order to reduce the refresh current. However, as the refresh interval extends, the cell having poor retention characteristic leaks electric charges out of the cell capacitor, causing damage to data.
In the related art, a repair technique of substituting a redundancy row for the cell having a poor retention characteristic has been used in order to improve the yield rate. However, since the redundancy row occupies the chip area, this scheme obstructs miniaturization of a chip size.
In another scheme, the cell having a poor retention characteristic may be relieved by additionally and concurrently refreshing the cell having the poor retention characteristic at a timing of an address having the most significant bit different from that of an address of the cell having the poor retention characteristic without using a redundancy. However, since the concurrent refresh scheme may need double the refresh current, additional circuit designs for a noise problem and a power supply capacity are may be needed.
In still another scheme, the cell having a poor retention characteristic may be relieved by restarting an addressing of a normal row after additionally performing the row-refresh of the cell having the poor retention characteristic at a timing of an address having the most significant bit different from that of an address of the cell having the poor retention characteristic. Some prior art suggests a scheme of storing a weak cell address and comparing an offset address obtained by inverting the most significant bit of a refresh shadow counter through an inverter with the weak cell address. According to the above technology, although the weak cells, which have a retention time equal to or longer than a half of a reference refresh interval and shorter than the reference refresh interval, may be easily relieved by inverting the most significant bit, an offset address generating circuit for the weak cells having a retention time less than the half reference refresh interval may not be easily implemented and a repair work according to a test result is very difficult.